IMPLEMENTATION AND DESIGNING OF LOW POWER SR FLIP-FLOP USING 45NM CMOS TECHNOLOGY

The design of low-power devices is currently an important area of research due to an increase in demand for portable devices. Since the MOS device is widespread, there is a great need for circuits to consume less power, especially for portable and handheld devices. A memory element consumes 70 percent of the total power in an integrated circuit. As flip-flop is the primary place of memory elements to use on any portable device, a wide attention to reduce energy consumption flip-flop will help reducing energy consumption in a large IC. In this paper, we designed a flip-flop with CMOS logic; It consumes less energy than conventional gates designed. Switching transistors occurs when applied input clock is applied. Proposed SR flip-flop synchronization, 0.7V power dissipation transient analysis and SR flip-flop different applications. This flip-flop is implemented using 45 nm in virtuoso cadence