Algorithmic and memory optimizations on multiple application mapping onto FPGAs

Field Programmable Gate Arrays (FPGAs) offer a low power flexible accelerator alternative due to their inherent parallelism. Reprogrammability, although it is their key feature, it is used almost exclusively on design time due to the constraints imposed by the modern CAD tools that require even days to run and tens of GB of RAM. In order to effectively utilize FPGAs on runtime we propose a novel methodology and the supporting tool flow that enable efficient mapping of multiple applications onto heterogeneous FPGAs. With the use of a floorplanning step, memory optimizations and custom memory allocators, we alleviate the constraints imposed by CAD tools, and provide a proof of concept that application mapping onto FPGAs can be done on runtime. Experimental results prove the efficiency of the introduced solution, as we achieve application’s mapping 40× faster on average compared to a state-of-art approach, without performance degradation and with 12× on average reduced memory usage