Update Logic Synthesis Objectives for Better Placement and Routing

This research is situated in the design of integrated circuits (ICs). ICs are virtually everywhere. They are physical implementations of digital circuits that perform some logical functionality. The steps involved in IC design are twofold. First in the Logic Synthesis step, an abstract representation of the logic functionality is designed in the form of a graph called a netlist. Second, this netlist needs to be further developed into a physically realizable model in a step called Physical Design (Placement and Routing). ICs consist of two main components: logic cells and interconnects. Logic cells are responsible for the data manipulation and interconnects transport the data between the logic cells. Both logic cells and interconnects amount to some delay that ultimately add up to determine the speed of the IC. Back in 1980, most of the delay was accounted for by the logic cells and interconnect delay was negligible. A consequence of this early imbalance is that the netlist is optimized to have as little logic cells as possible. However, as IC technology progressed, the delay in logic cells decreased significantly and the delay in interconnects became more important. Today, the speed of an IC is considerably impacted by lengthy interconnects. Despite this shift in delay causes, the general objective of minimizing the amount of logic cells has not changed. In this poster, we argue that the netlist should be optimized for different, yet unknown, objectives. This is done by giving a simple example that shows a discrepancy between minimizing the amount of logic cells and optimizing speed