Compiler for the Versat reconfigurable architecture

This work describes the implementation of a compiler for Versat, a Coarse Grained Reconfigurable Array (CGRA). Before this work, Versat was only programmable in its assembly language. The developed compiler uses a simple and high-level Intermediate Representation (IR), contrasting with the complex and low-level IR found in compiler frameworks such as GCC or LLVM. Our IR is more easily translated into hardware datapaths, which are mapped to Versat partial reconfiguration instructions. The language syntax is a small subset of the C++ language, for the compiler is used only for sequences of loop nests containing operations on data arrays, as found in the target applications: digital filters, transforms and big data algorithms such as deep learning and k-means clustering. Experimental results show fast compilation time, and code size / execution time similar to handwritten assembly code