A new systematic GDI circuit synthesis for low power ASIC circuit design

The advances in the new process technology characteristically come with a multitude of new design variables and hence a new set of challenges for the designers to understand the impact of circuit design. During the last decade, widespread deliberations have been specified to the usage of Gate Diffusion Input (GDI) networks in the design of digital core systems; however the logic design has been constructed using transistor-level. Till now there is no specific approach is available for synthesizing GDI circuit that incorporated the impact of signal arrangement and circuit technology. Creation of standard cell library for GDI technique becomes an utmost imperative. In this research work, a regimented synthesis algorithm have been proposed to minimize power and augment performance of the digital circuits through two approaches MUX based decomposition algorithm and Binary Decision Diagram (BDD). The primitive nodes are implemented by GDI logic and CMOS logic for level restoration circuit. This research work is targeted to design sub-micron GDI library which is suitable for the 180nm and 90nm 6-metal layer CMOS n-well process which is offered by MOSIS. The principal focus is to engender a comprehensive library including the core number of essential primitive cells, depicting the detailed layout and transistor-level schematic views of every cell in180nm and 90nm process, in order to use them as a completely synthesizable library. The signal connectivity models for GDI are presented using MUX and BDD approach. The synthesis of ISCAS Combinational bench mark circuit in CMOS, PTL and GDI technique is also examined in this work along with buffer inclusion procedure for GDI technique