WIDE-RANGE LOW-POWER 1.12PS JITTER DELAY LOCKED LOOP BY A NOVEL LOCK-DETECTION TECHNIQUE

Abstract Analog DLLs are formed of a voltage-controlled delay line (VCDL), a phase detector (PD), a charge pump (CP), and a loop filter. Phase Detector is the main component in designing DLLs, in this paper a sensitivity with small dead-zone and reduced number of transistor-based Master-Slave DFF and wide range compatible charge pump is presented. A CMOS delay locked loop design was done and simulated in BSIM3 model of level 49 H-Spice parameters in 180 nm, the supply voltage 1.8V and aim of achieving post-layout simulation and dead zone under 100 ps which resulted in 3.3 mW power consumption and 1.01 ps RMS jitter at 166 MHz. The post-layout results show that in a 130×250 µm2 area, the jitter of DLL in comparison to similar works is reduced as well