QCA DESIGN OF SRAM CELL USING REVERSIBLE ADDRESS DECODER

A memory unit is a gathering of capacity cells together with related circuits expected to change data all through the gadget. Memory cells which can be gotten to for data exchange to or from any coveted arbitrary area is called Random Access Memory (RAM). A decoder is an imperative part of memory, for address disentangling and encoding. The sizes of Complementary Metal Oxide Semiconductor (CMOS) transistor continue contracting to build the thickness on chip as per Moore's Law. The scaling influences the gadget execution because of requirements like warmth dissemination and power utilization. A Quantum spot Cellular Automaton (QCA) is another option to CMOS. It offers higher speed, bring down power utilization, and higher thickness. In non reversible doors some measure of energy misfortune is included. Enthusiasm for reversible rationale offers lessened warmth dispersal and expands the speed. It is another transistor less calculation in nanotechnology. In this venture propose a SRAM CELL configuration utilizing Feynman gate based decoder.It gives reversibility and territory minimization. QCA architect instrument has been utilized to approve the execution of reversible decoders. Keywords-