Fermilab Physics Department Fastbus TDC Module

A prototype 64 channel Fastbus TDC built at Fermilab is described. The module features a full custom CMOS four channel gated integrator chip. One level of analog buffering at the inputs is implemented on chip. A four event deep output queue at the bus interface allows a high event rate with low dead time. Each channel can record up to two hits per event. With an occupation rate of 10%, the module can operate at 40,000 events per second with dead time on the order of 15%. The TDC operates in common stop mode with a full scale of 1-mu-sec and a resolution of 1 nsec