DUTY CYCLE CORRECTOR USING PULSE WIDTH MODULATION

In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW