This paper analyzes the patterns of the Monte Carlo data for a large number of variables and minterms, in order to characterize the circuit path length behavior. We propose models that are determined by training process of shortest path length derived from a wide range of binary decision diagram (BDD) simulations. The creation of the model was done use of feed forward neural network (NN) modeling methodology. Experimental results for ISCAS benchmark circuits show an RMS error of 0.102 for the shortest path length complexity estimation predicted by the NN model (NNM). Use of such a model can help reduce the time complexity of very large scale integrated (VLSI) circuitries and related computer-aided design (CAD) tools that use BDDs
Efficient algorithms are presented to generate approximate expressions for transfer functions and ch...
This letter addresses the issue of learning shortest paths in complex networks, which is of utmost i...
. Despite more than a decade of experience with the use of standardized benchmark circuits, meaningf...
When binary decision diagrams are formed from uniformly distributed Monte Carlo data for a large num...
This paper describes a neural network approach that gives an estimation method for the space complex...
In this work, we analyzes the relationship between randomly generated Boolean function complexity an...
The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes ...
Power disspiation is a growing concern in VLSI circuits. In this work we model the data dependence o...
Abstract — Process variations in digital circuits make sequential circuit timing validation an extre...
Due to the impact of process variations, timing characteristics of chip is uncertain due to uncertai...
A Monte Carlo based approach is proposed capable of identifying in a non-enumerative and scalable ma...
In this paper, the classic wire-length estimation problem is addressed and a new statistical wire-le...
[Please see the article via the link above for the full abstract including mathematical formulae]. W...
We address the classic wire-length estimation problem and propose a new statistical wire-length esti...
We present methods to generate a Binary Decision Diagram (BDD) with minimum expected path length. A ...
Efficient algorithms are presented to generate approximate expressions for transfer functions and ch...
This letter addresses the issue of learning shortest paths in complex networks, which is of utmost i...
. Despite more than a decade of experience with the use of standardized benchmark circuits, meaningf...
When binary decision diagrams are formed from uniformly distributed Monte Carlo data for a large num...
This paper describes a neural network approach that gives an estimation method for the space complex...
In this work, we analyzes the relationship between randomly generated Boolean function complexity an...
The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes ...
Power disspiation is a growing concern in VLSI circuits. In this work we model the data dependence o...
Abstract — Process variations in digital circuits make sequential circuit timing validation an extre...
Due to the impact of process variations, timing characteristics of chip is uncertain due to uncertai...
A Monte Carlo based approach is proposed capable of identifying in a non-enumerative and scalable ma...
In this paper, the classic wire-length estimation problem is addressed and a new statistical wire-le...
[Please see the article via the link above for the full abstract including mathematical formulae]. W...
We address the classic wire-length estimation problem and propose a new statistical wire-length esti...
We present methods to generate a Binary Decision Diagram (BDD) with minimum expected path length. A ...
Efficient algorithms are presented to generate approximate expressions for transfer functions and ch...
This letter addresses the issue of learning shortest paths in complex networks, which is of utmost i...
. Despite more than a decade of experience with the use of standardized benchmark circuits, meaningf...