Optimization of IFS Subroutine LAITRI on Intel Knights Landing

The landscape of HPC architectures has undergone signi cant change in the last few years. Notably, the Intel Xeon Phi architecture features a 512 bit wide vector register allowing ne-grained parallelism, with a marked improvement in memory/cache speeds in the Knights Landing variant over the original Knights Corner version. Complexity of optimization is increased due to the great variety of hardware features, where cache considerations become fundamentally important. The optimization process is greatly facilitated in this regard by the Intel Advisor tool, which not only allows traditional roofline analysis, but also new roofline variations speci c to each cache level - the `cache-aware' roofline model (CARM). The Exascale-driving ESCAPE project is motivated by reducing time/energy costs of numerical weather prediction in part by investigation of `mini-app/dwarf' performance on emerging hardware. The LAITRI subroutine of IFS is one of the `seven dwarves of HPC weather codes'. It accounts for about 4% of the total runtime of IFS in production. We investigate various optimization strategies (using coarse and ne-grained parallelism among other ideas) for speeding up LAITRI. The CARM implemented by the Intel Advisor allows realistic evaluation of actual/potential performance gain