The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, makin...
Nowadays, people are increasingly relying on the internet and expecting ever faster connectivity to ...
Future technologies will allow the integration of hundreds of billions of transistors on a single ch...
grantor: University of TorontoIn partitioned FPGA designs such as those in FPGA emulation ...
On-chip global communication is required for data and control transfers across various modules on th...
A bidirectional serial link on-chip implementation is going to be assessed so as to set the option o...
The design of a 4 Gbps serial link transceiver in 0.35µm CMOS process is presented. The major factor...
In this paper, the design and applications of highspeed interconnect transceivers are presented. Ser...
Abstract—This paper presents a set of circuit techniques to achieve high data rate point-to-point co...
The data rate of global on-chip interconnects (up to 10 mm) is limited by a large distributed resist...
Global on-chip data communication is becoming a concern as the gap between transistor speed and inte...
In this paper, the equalization techniques for highspeed interconnect transceivers are discussed. Se...
As data and computing systems get larger with more elements composing a single system, streamlined c...
The need for efficient interconnect architectures beyond the conventional time-division multiplexing...
The use of serializers and deserializers in SerDes devices is a compulsory requirement for chip to c...
University of Minnesot Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: Dr...
Nowadays, people are increasingly relying on the internet and expecting ever faster connectivity to ...
Future technologies will allow the integration of hundreds of billions of transistors on a single ch...
grantor: University of TorontoIn partitioned FPGA designs such as those in FPGA emulation ...
On-chip global communication is required for data and control transfers across various modules on th...
A bidirectional serial link on-chip implementation is going to be assessed so as to set the option o...
The design of a 4 Gbps serial link transceiver in 0.35µm CMOS process is presented. The major factor...
In this paper, the design and applications of highspeed interconnect transceivers are presented. Ser...
Abstract—This paper presents a set of circuit techniques to achieve high data rate point-to-point co...
The data rate of global on-chip interconnects (up to 10 mm) is limited by a large distributed resist...
Global on-chip data communication is becoming a concern as the gap between transistor speed and inte...
In this paper, the equalization techniques for highspeed interconnect transceivers are discussed. Se...
As data and computing systems get larger with more elements composing a single system, streamlined c...
The need for efficient interconnect architectures beyond the conventional time-division multiplexing...
The use of serializers and deserializers in SerDes devices is a compulsory requirement for chip to c...
University of Minnesot Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: Dr...
Nowadays, people are increasingly relying on the internet and expecting ever faster connectivity to ...
Future technologies will allow the integration of hundreds of billions of transistors on a single ch...
grantor: University of TorontoIn partitioned FPGA designs such as those in FPGA emulation ...