IMPLEMENTATION OF SDC - SDF ARCHITECTURE FOR RADIX-4 FFT

Very large scale integration and Digital signal processing are the very crucial technologies from the last few decades. DSP applications require high performance, low area and low power VLSI circuits. This paper is discussing about FFT which is one of the vital component in the digital signal processing. In this Paper, we propose a single path delay commutator–feedback (SDC-SDF) Architecture for Radix-4 FFT and presented its simulation and synthesis results. The Radix-4 FFT architecture consists of log4 N-1 SDC Stages and 1 SDF stage. Previously, the radix-2 SDC-SDF (Single path delay commutator-feedback) FFT architecture was includes log2 N-1 SDC Stages and 1 SDF stage. The proposed Radix-4 SDC-SDF architecture reduces the number of multiplications and additions as well as number of stages which achieves reduced area and low power. The resultant architecture is simulated using Modelsim, design verification and synthesis results are done using Xilinx ISE. The proposed architecture is compared with Radix-2 SDC-SDF FFT and it can achieve less area as well as low power consumption