Signal processing applications which are iterative in nature are best represented by data flow graphs (DFG). In these applications, the maximum sampling frequency is dependent on the topology of the DFG, the cyclic dependencies in particular. The determination of the iteration bound, which is the reciprocal of the maximum sampling frequency, is critical in the process of hardware implementation of signal processing applications. In this paper, a novel technique to compute the iteration bound is proposed. This technique is different from all previously proposed techniques, in the sense that it is based on the natural flow of tokens into the DFG rather than the topology of the graph. The proposed algorithm has lower run-time complexity than a...
Recently, Goldberg proposed a new approach to the maximum network flow problem. The approach yields ...
Synchronous dataflow (SDF) semantics are well-suited to representing and compiling multirate signal ...
Abstract. Regular arrays of processing elements in VLSI have proved to be suitable for high-speed ex...
Digital signal processing algorithms are described by iterative data-flow graphs where nodes represe...
Rate-optimal scheduling of iterative data-flow graphs requires the computation of the iteration peri...
This paper builds upon research by Lee [1] concerning the token flow model, an analytical model for ...
The iterative algorithm is widely used to solve instances of data-flow analysis problems. The algori...
Abstract. Loop identification is an essential step of control flow analysis in decompilation. The Cl...
Many computation-intensive or recursive applications commonly found in digital signal processing and...
Time-critical sections of multi-dimensional problems, such as image processing applications, are in ...
This paper addresses the issue of determining the iteration bound for a synchronous data flow graph ...
Loop identification is an essential step of control flow analysis in decompilation. The Classical al...
Synchronous dataflow (SDF) semantics are wellsuited to representing and compiling multirate signal p...
A large class of nonlinear dynamic adaptive systems such as dynamic recurrent neural networks can be...
We discuss the implementation of network flow algorithms in floating point arithmetic. We give an e...
Recently, Goldberg proposed a new approach to the maximum network flow problem. The approach yields ...
Synchronous dataflow (SDF) semantics are well-suited to representing and compiling multirate signal ...
Abstract. Regular arrays of processing elements in VLSI have proved to be suitable for high-speed ex...
Digital signal processing algorithms are described by iterative data-flow graphs where nodes represe...
Rate-optimal scheduling of iterative data-flow graphs requires the computation of the iteration peri...
This paper builds upon research by Lee [1] concerning the token flow model, an analytical model for ...
The iterative algorithm is widely used to solve instances of data-flow analysis problems. The algori...
Abstract. Loop identification is an essential step of control flow analysis in decompilation. The Cl...
Many computation-intensive or recursive applications commonly found in digital signal processing and...
Time-critical sections of multi-dimensional problems, such as image processing applications, are in ...
This paper addresses the issue of determining the iteration bound for a synchronous data flow graph ...
Loop identification is an essential step of control flow analysis in decompilation. The Classical al...
Synchronous dataflow (SDF) semantics are wellsuited to representing and compiling multirate signal p...
A large class of nonlinear dynamic adaptive systems such as dynamic recurrent neural networks can be...
We discuss the implementation of network flow algorithms in floating point arithmetic. We give an e...
Recently, Goldberg proposed a new approach to the maximum network flow problem. The approach yields ...
Synchronous dataflow (SDF) semantics are well-suited to representing and compiling multirate signal ...
Abstract. Regular arrays of processing elements in VLSI have proved to be suitable for high-speed ex...