Implementation of Unsigned Multiplier Using Area-Delay-Power Efficient Adder

Multiplication and addition are most widely and oftenly used arithmetic computations performed in all digital signal processing applications. Multiplication is the basic arithmetic operation which is present in many part of the digital computer especially in signal processing systems such as graphics and computation system. It requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. This paper deals with the basic multiplier that is shift and add multiplier. Accurate operation of the shift and add multiplier is mainly influenced by the performance of the adder. So performance of the adder enhances the performance of the multiplier. Hence, to design a better architecture the basic adder blocks must have reduced delay time consumption and area efficient architectures. This paper, involves the implementation of unsigned multiplier using area, delay and power efficient adder. This design will be developed using Verilog programming language and implementing using Field Programmable Gate Array (FPGA) platform