D7.6: Best Practice Guides for New and Emerging Architectures

The Work Package 7 ‘Application Enabling and Support’ provides applications enabling support for HPC applications codes that are important for European academic and/or industrial researchers to ensure that these applications can effectively exploit current and future PRACE systems. Applications are selected for enabling via calls such as PRACE Preparatory Access (for Tier-0 or Tier-1), or SHAPE (SME HPC Adoption Programme in Europe). This applications enabling activity uses the most promising tools, algorithms and standards for optimisation and parallel scaling that have recently been developed through research and experience in PRACE and other projects. Through the applications-enabling work, the Work Package 7 develops specific expertise on most – if not all – of the architectures which make up the European HPC system. Technical results obtained within this Work Package have been disseminated though many technical whitepapers freely available on the PRACE RI web site. In addition to this enabling work on existing systems, the Work Package also progresses the technical work needed to ensure that key applications are able to use future PRACE Exascale systems, and investigate the tools, languages and libraries needed to exploit future PRACE Exascale systems. One of the main objectives of the Work Package is to support European HPC research communities through the provision of Best Practice Guides, benchmarks, and example parallel codes. The successful series of Best Practice Guides has been initiated in PRACE-1IP and has been continuously extended since then: PRACE-1IP provided four Best Practice Guides for PRACE Tier-0 systems (JUGENE, Curie, Cray XE and IBM Power) that cover programming techniques, compilers, tools and libraries. PRACE-2IP added a generic guide about the x86 architecture and a Best Practice Guide for the SuperMUC system, together with a series of seven Best Practice Mini-Guides for other architectures which are important at Tier-1 to allow European researchers to make efficient use of these systems. PRACE-3IP supplemented these with Best Practice Guides about Blue Gene/Q and IBM Power 775 and provided updates of the Curie and the Cray XE guide, which was renamed into Cray XE/XC. PRACE-4IP Task 7.3.B added new guides about Knights Landing and Haswell/Broadwell and provided updates of the Intel® Xeon Phi™ and the GPGPU Best Practice Guides. Topics for these Best Practice Guides include: optimal porting of applications (e.g., choice of numerical libraries and compiler options); architecture specific optimisation and scaling techniques; optimal system environment (e.g., tuneable system parameters, job placement and optimised system libraries); debugging tools, performance analysis tools and programming environment. This report describes the process which led to the Best Practice Guides and the structure of the guides. For the Best Practice Guides itself we refer to the online versions on the PRACE RI web site