New Interconnection Topology for Network on Chip

The architecture of networks on chip (NOC) highly affects the overall performance of the system on chip (SOC). A new topology for chip interconnection called Torus connected Rings is proposed. Due to the presence of multiple disjoint paths between any source and destination pair, this topology exhibits high fault tolerance capability. The proposed routing method can tolerate faults adaptively. TCR is simple in design and highly scalable. The detailed design and topological parameters are compared with alternate topologies