Delay Analysis of VLSI Interconnects for High-Speed Applications

In this paper, dynamic crosstalk is analyzed for coupled on-chip VLSI interconnects in different conditions. The proposed work has taken the MOS transistor analytical expressions. This work calculated the transition delays and different timings of the interconnect aggressor and interconnect victim drivers for in-phase switching and out of-phase switching. All the calculated results are compared with simulations in SPICE. The average error in the transmission delay using SPICE is 2.02 and 3.274% for the interconnect aggressor and interconnect victim buffers for in-phase switching, respectively. The average errors in the same are 2.3 and 1.87% for out-phase switching events. In this paper, dynamic crosstalk is analyzed for coupled on-chip VLSI interconnects in different conditions. The proposed work has taken the MOS transistor analytical expressions. This work calculated the transition delays and different timings of the interconnect aggressor and interconnect victim drivers for in-phase switching and out of-phase switching. All the calculated results are compared with simulations in SPICE. The average error in the transmission delay using SPICE is 2.02 and 3.274% for the interconnect aggressor and interconnect victim buffers for in-phase switching, respectively. The average errors in the same are 2.3 and 1.87% for out-phase switching events