Design and Implementation of Adiabatic based Low Power Logic Circuits

With the growing technology and markets demand necessitated the immediacy efforts in the field of development of low power VLSI design circuit. Though there are many approaches available that can be used to reduce the power/energy dissipation in conventional CMOS circuit which may include, reducing the supply voltage, or decreasing the node capacitances and minimizing the switching activities with efficient charge recovery logic. But all these reducing method have certain physical limitations, yet their limiting values are near but still they are in debatable. In this scenario many researchers are trying to adopt different optimization and energy conservation principle for VLSI circuit which led to the development of a new classical approach of switching logic knows as adiabatic switching logic. The basic principle in adiabatic logic circuits is to slow down the logic transition varying from logic 1 to logic 0 and vice versa, aiming in reducing the power dissipation. Many different approaches/ techniques are proposed for implementing adiabatic logic circuits among which, PFAL is one of those techniques which positively promise assisting in the power issues. This paper present the simulation of NAND and NOR logic gate by CMOS and PFAL logic moreover with the help of simulated result by OrCAD PSPICE tool, it can be shown that the NAND & NOR used with adiabatic logic can reduce the power dissipation effectively than conventional CMOS circuit.Paper available at https://www.irjet.net/archives/V2/i2/Irjet-v2i291.pd