A Successive Method of Flashing for ADC Networks

In spite of being fastest Flash ADC isn’t much popular due to its huge siege and large power consumption. To overcome these problems half flash ADC is introduced in which A/D conversion is done in two steps. Say for an 8-bit system, first the higher 4 bits and then lower 4 bits. So total comparators required is 32. Besides two separate encoder circuit consisting of logic gates and diodes, a 4-bit DAC, a differential amplifier, track and hold circuit etc. is required. So, this system isn’t small enough for implementing inside any microcontroller or small digital devices. This paper shows an advanced architecture of A/D converter based on the theory of half flash. The difference is that the convention will happen bit wise. First MSB, then the value of the MSB will be used to generate 2nd MSB. Just a comparator and a differential amplifier is required to generate each bit. No encoder circuit and DAC are required. So, for a n-bit conversion just (2n-1) operational amplifier is required. So, for a 8 bit ADC just 15 op-amp is required. Less amount of op-amp and elimination of encoders and DAC makes the circuit so much smaller and less power consuming and relatively faster which makes it suitable for implementing it inside any microcontroller. This paper explains the contusion, operating principle, errors and process of eliminating errors of a 3-bit ADC