Double-gate FinFET is identified as a prospect in fulfilling the demands required in replacing the current conventional planar MOSFETs due to several advantages. Specifically in its scalability, reduced leakage current, high drive current, with steep subthreshold swing, subsequently improving the ION/IOFF ratio, thus reducing the power consumption of the device. The susceptibility towards the electrical performance of the device is exposed due to the process parameter variations from the device miniaturization. This research work is aimed towards optimizing the process parameter variation towards the device characteristics with several appropriate statistical methods used. Taguchi statistical method, the Taguchi-based Grey Relational Analys...
In this study, the effect of process parameters on the threshold voltage (Vth) and leakage current (...
The optimization of 45nm NMOS device was studied using Taguchi Method. This method was used to anal...
A 32nm top-gated bilayer Graphene PMOS transistor was optimized and analyzed to find the optimum val...
The impact of the optimization using Taguchi statistical method towards the electrical properties of...
The conventional transistor device has been effective to provide for continual improvements in integ...
This paper studies various Double-Gate (DG) FinFET structures optimized for better "off state &...
This paper studies various Double-Gate (DG) FinFET structures optimized for better “off state” and “...
The steady miniaturization of the conventional (planar bulk) Metal Oxide Semiconductor Field Effect ...
This study describes a proposed method to determine the most optimal level of process parameters, co...
Random parameter variations have been an influential factor that deciding the performance of a metal...
In this paper, effect of the process parameters variation on response characteristics such as thresh...
Simulations of a computer-generated downscaled device at 14nm gate length of p-type MOSFET is confer...
In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant...
This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs...
Technology scaling below 22 nm has brought several detrimental effects such as increased short chann...
In this study, the effect of process parameters on the threshold voltage (Vth) and leakage current (...
The optimization of 45nm NMOS device was studied using Taguchi Method. This method was used to anal...
A 32nm top-gated bilayer Graphene PMOS transistor was optimized and analyzed to find the optimum val...
The impact of the optimization using Taguchi statistical method towards the electrical properties of...
The conventional transistor device has been effective to provide for continual improvements in integ...
This paper studies various Double-Gate (DG) FinFET structures optimized for better "off state &...
This paper studies various Double-Gate (DG) FinFET structures optimized for better “off state” and “...
The steady miniaturization of the conventional (planar bulk) Metal Oxide Semiconductor Field Effect ...
This study describes a proposed method to determine the most optimal level of process parameters, co...
Random parameter variations have been an influential factor that deciding the performance of a metal...
In this paper, effect of the process parameters variation on response characteristics such as thresh...
Simulations of a computer-generated downscaled device at 14nm gate length of p-type MOSFET is confer...
In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant...
This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs...
Technology scaling below 22 nm has brought several detrimental effects such as increased short chann...
In this study, the effect of process parameters on the threshold voltage (Vth) and leakage current (...
The optimization of 45nm NMOS device was studied using Taguchi Method. This method was used to anal...
A 32nm top-gated bilayer Graphene PMOS transistor was optimized and analyzed to find the optimum val...