A Redundant Binary-to-Thermometer Decoder Design

This chapter presents a test-chip implementation of a CML 4-to-15 redundant binary-to-thermometer decoder in a 12 bit 180 nm CMOS DAC. The relative increase of the occupied area due to using the new concept is estimated to be as low as 1%, which suggests that the correction methods using the new redundant decoder should be very efficient. Measurement results show that even for such a small increase in the required design resources, a considerable improvement in the DAC performance can be achieved. The measured improvement in INLmax is 1.5 LSB, while the measured improvement in SFDR is 5.7 dB for fin = 6.8 MHz and Fs = 100 MS/s. The presented decoder can be used with either mapping DAC correction methods or DEM DAC correction methods.