A 60 GHz Down-conversion Passive Mixer in 65 nm CMOS Technology

A passive down-conversion mixer in a 65nm buck CMOS process has been presented. The proposed mixer is consisted of a mixer-core and a folded OTA buffer. The mixer has a 3-dB bandwidth of 57~66 GHz, with a conversion gain of −2.7 ~ −5.4 dB. It requires a LO level of −5 dBm. The isolation between LO and RF ports is 10 dB. The total power consumption of the mixer is 1.4 mW, and the chip area is 0.4 mm 2