Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding

Numerous modern applications in various fields, such as communication and networking, multimedia, encryption, etc., impose extremely high demands regarding performance while at the same time requiring low energy consumption, low cost, and short design time. Often these very high demands cannot be satisfied by application implementations on programmable processors. Massively parallel multi-processor hardware accelerators are necessary to adequately serve these applications. The accelerator design for such applications has to decide both the micro-architectures of particular processors and the multi-processor system macro-architecture. Due to complex tradeoffs between the micro-architectures and macro-architectures, the micro- and macro-architecture design has to be performed in combination and not in separation, as with the state-of-the-art design methods and tools. To ensure effective and efficient application implementations, an adequate design space exploration (DSE) is necessary. It has to construct and analyze several most promising micro- and macro-architecture combinations and to select the best of them. In this paper, we will show that the lack of such a design space exploration would not only make it very difficult to satisfy the ultra-high performance demands of such applications, but it would also seriously degrade the accelerator quality in other design dimensions. To adequately design the multi-processor accelerators for highly-demanding applications, we proposed a quality-driven model-based design method. This paper is devoted to the processor architecture exploration and synthesis of the heterogeneous multi-processor system being one of the most important aspects of our method. The method is implemented in our automatic DSE tool. Using our DSE tool and the LDPC decoding application as a case study, we performed an extensive experimental research of automatic synthesis of various hardware multi-processors for LDPC decoding to show various complex issues and tradeoffs in the processor architecture design, and to demonstrate the high quality of our method and DSE tool in relation to this aspect.