Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing

There is much focus on timing error resilience for the speed critical paths of processors. In the context of growing parameter variations with technology scaling and voltage scaling, resilience helps to ensure functional correctness. Moreover it allows the chip to stretch its operating voltage and frequency beyond the conventional limits to meet the demand for high performance and low power. Conventionally, timing error resilience is achieved through variation tolerant circuitry at the cost of undesirable power, area and throughput overheads. Such overheads are aggravated by the presence of large number of critical timing paths in the design. In this paper, we propose a slack-aware timing margin redistribution technique for error resilience using time borrowing error avoidance flip-flops (EAFFs) while minimizing overheads. The proposed algorithm designs the processor critical paths ground up by inserting EAFFs at places where positive slack is available in the subsequent fan-out stage. Experiment results on an industrial processor design show that a timing margin improvement of 11% of the clock period can be achieved on 64% of the critical paths and a 55% timing margin on 45% of the critical paths without any throughput degradation. The area and power overheads of the additional flip-flops are 0.2% and 5.4%, respectively.