Scalable optical packet switch architecture for low latency and high load computer communication networks

High performance computer and data-centers require PetaFlop/s processing speed and Petabyte storage capacity with thousands of low-latency short link interconnections between computers nodes. Switch matrices that operate transparently in the optical domain are a potential way to efficiently interconnect 1000's of inputs/outputs, complying the end-to-end latency (~1 µs) of these systems. Current rearrangeable non-blocking switches architectures (Benes, Omega, etc..) have a reconfiguration time (expressed in clock-cycles) at most of Mog2(N), N is the number of nodes. Assuming a clock cycle of 1 ns, it follows that the latency requirement cannot be met for N >; 100. Moreover, being the switch disable during this time, the packets are either lost or buffered, limiting the maximum load of the system. In this work we present a new strictly non-blocking switch architecture with a contention resolution sub system. Key point is that the new architecture supports highly distributed control that allows for reduction of the switching time to few nanoseconds regardless the N input/output nodes. Thus, the architecture can meet the latency requirement without limiting the load of the system