Model order reduction and sensitivity analysis

The electronics industry provides the core technology for numerous industrial innovations. Progress in the area of microelectronics is highlighted by several milestones in chip technology, for example microprocessors and memory chips. The ongoing increase in performance and memory density would not have been possible without the extensive use of computer simulation techniques, especially electronic circuit simulation. The basis of the latter is formed by a sound framework of methods from the area of numerical methods. In recent years, the demands on the capabilities of circuit simulation have become even more stringent. Circuit simulators have become the core of all simulations within the electronics industry. Crosstalk effects in interconnect structures are modeled by large extracted RLC networks. Also, substrate effects that start playing a crucial role in determining the performance are modeled by extracting, again, large resistive or RC networks. New algorithms are needed to cope with such situations that are extremely crucial for designers. The complexity caused by these parasitic extractions must be reduced to facilitate the simulation of the circuit while preserving accuracy. Fortunately, highly accurate parasitic extraction is not necessary for all parts of the design. Each layout contains critical blocks or paths whose timing and performance is crucial for the overall functionality of the chip. High precision interconnect modeling must be used for these circuit parts to verify the functionality of the design. On the other hand, there is interconnect outside of critical paths which adds to the complexity but whose exact model is not necessary and can be simplified. For the critical paths a so-called sensitivity analysis can bring a major achievement in speed-up, by automatically determining the critical parasitic elements that provide the most dominant influence. Another important aspect is the fact that there is an increasing deviation between design and manufacturing. Due to the ever decreasing feature sizes in modern chips, deviations from the intended dimensions are becoming more probable. Designers need to cope with this, and design the circuits in such a way that a deviation from intended dimensions does not alter the functionality of the circuit. In order to investigate this properly, one needs to assume that all components can possibly be slightly different after manufacturing.The effects this has on the performance of the circuit can be studied by introducing many thousands or even millions of parameters, describing the deviations, and performing a sensitivity analysis of the circuit w.r.t. parameter changes. The aforementioned problems form the inspiration for the study in this thesis. Sensitivity analysis is crucial for the correctness of virtual design environments based on electronic circuit simulators, and gives designers insight in how to alter the designs in order to guarantee more robustness with respect to variability in the design. The problem is that a thorough sensitivity analysis requires derivatives of the solution with respect to a large amount of parameters. This is not feasible using classical methods, being far too time-consuming for modern circuits. Recently proposed methods using the adjoint problem to calculate sensitivities are far more efficient, and these form the basis for our methodology. Our work has concentrated on making such methods even more efficient, by mixing them with concepts from the area of model order reduction. This leads to very efficient, robust and accurate methods for sensitivity analysis, even if the underlying circuit is large and the number of parameters is excessive