Add to ORKGAdaptive circuit techniques enable modification of power-performance efficient circuit operation. Yet it is unclear if such techniques remain effective in modern deep-submicron CMOS. In this paper we examine the technological boundaries of supply voltage scaling and body biasing in 45nm low-power CMOS. We demonstrate that there exists an effective tuning range for power-performance and performance variability control. Our analysis is supported by ring oscillator test-chip measurements
The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO’s) is investigated in orde...
Device scaling has resulted in large scale integrated, high performance, low-power, and low cost sys...
As technology scales down in order to meet demands of more computing power per area, a variety of ch...
Adaptive circuit techniques enable modification of power-performance efficient circuit operation. Ye...
In this paper we examine the expectations and limitations of design technologies such as adaptive vo...
Technology scaling improves the energy, performance, and area of the digital circuits. With further ...
We examine technology constraints on tuning active power and delay using adaptive voltage scaling (A...
In this chapter, we concentrate on technological quantitative pointers for adaptive voltage scaling ...
Abstract-In this paper we examine technology constraints on tuning active power and delay using adap...
The advent of deep submicron technologies brings new challenges to digital circuit design. A reduced...
Lowering supply voltage is still the most effective technique to reduce dynamic power, and Vdd is be...
In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presen...
The progression of technology has required smaller devices to achieve faster circuits and more power...
We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant ...
Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum spe...
The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO’s) is investigated in orde...
Device scaling has resulted in large scale integrated, high performance, low-power, and low cost sys...
As technology scales down in order to meet demands of more computing power per area, a variety of ch...
Adaptive circuit techniques enable modification of power-performance efficient circuit operation. Ye...
In this paper we examine the expectations and limitations of design technologies such as adaptive vo...
Technology scaling improves the energy, performance, and area of the digital circuits. With further ...
We examine technology constraints on tuning active power and delay using adaptive voltage scaling (A...
In this chapter, we concentrate on technological quantitative pointers for adaptive voltage scaling ...
Abstract-In this paper we examine technology constraints on tuning active power and delay using adap...
The advent of deep submicron technologies brings new challenges to digital circuit design. A reduced...
Lowering supply voltage is still the most effective technique to reduce dynamic power, and Vdd is be...
In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presen...
The progression of technology has required smaller devices to achieve faster circuits and more power...
We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant ...
Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum spe...
The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO’s) is investigated in orde...
Device scaling has resulted in large scale integrated, high performance, low-power, and low cost sys...
As technology scales down in order to meet demands of more computing power per area, a variety of ch...