DDL-based Calibration Techniques for Timing Errors in Current-Steering DAC's

Abstract-Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two Digital-Delay-Line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance. The simulation results of a phase detector, the key circuit in these two calibration techniques, are given. This circuit is implemented in a CMOS 0.18µm process