A new approximation algorithm is presented for the efficient handling of large macro-cell placement problems. The algorithm combines simulated annealing with new features based on a hierarchical approach and a divide-and-conquer technique. Numerical results show that these features can lead to a considerable increase in efficiency of the placement algorithm without loss of effectiveness
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
Practical analog layout synthesis techniques have been the subject of active research for the past t...
The standard cell placement problem has been extensively studied in the past twenty years. Many appr...
A new approximation algorithm is presented for the efficient handling of large macro-cell placement ...
In this paper we show that the computation time associated with the standard annealing algorithm for...
Conventional simulated annealing algorithm, which works on the flattened circuit, has a very large s...
Macro cell placement is an integral part of VLSI design. Existing placement techniques do not use a ...
Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this probl...
A new genetic algorithm for the macro cell placement problem is presented. The algorithm is based on...
Abstract-Parallel algorithms with quality equivalent to the simu-lated annealing placement algorithm...
In this paper we present a novel force-directed placement algorithm, which is used to solve macro-ce...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a c...
The algorithms and the implementation of a new macro/custom cell chip-planning. placement, and globa...
We introduce the new optimization method of Simulated Evolution (SE), which is designed to find near...
Parallel algorithms developed for CAD problems today suffer from three important drawbacks. First, t...
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
Practical analog layout synthesis techniques have been the subject of active research for the past t...
The standard cell placement problem has been extensively studied in the past twenty years. Many appr...
A new approximation algorithm is presented for the efficient handling of large macro-cell placement ...
In this paper we show that the computation time associated with the standard annealing algorithm for...
Conventional simulated annealing algorithm, which works on the flattened circuit, has a very large s...
Macro cell placement is an integral part of VLSI design. Existing placement techniques do not use a ...
Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this probl...
A new genetic algorithm for the macro cell placement problem is presented. The algorithm is based on...
Abstract-Parallel algorithms with quality equivalent to the simu-lated annealing placement algorithm...
In this paper we present a novel force-directed placement algorithm, which is used to solve macro-ce...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a c...
The algorithms and the implementation of a new macro/custom cell chip-planning. placement, and globa...
We introduce the new optimization method of Simulated Evolution (SE), which is designed to find near...
Parallel algorithms developed for CAD problems today suffer from three important drawbacks. First, t...
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
Practical analog layout synthesis techniques have been the subject of active research for the past t...
The standard cell placement problem has been extensively studied in the past twenty years. Many appr...