According to an example embodiment, there is a testing device for testing a phase locked loop having a power supply input. The testing device comprises a power supply unit for providing a power supply signal VDD having a variation profile to the power supply input of the phase locked loop, wherein a width and height of said variation profile are formed in such a way, that the voltage controlled oscillator is prevented from outputting an oscillating output signal. There is a means for disabling a feedback signal to a phase comparator of the phase locked loop such that said phase locked loop is operated in an open loop mode, and a meter for measuring a measurement signal of the phase locked loop, while said power supply signal is provided to ...
A method and apparatus for testing analogue or RF circuitry, wherein the power supply VDD is ramped ...
DE 2854039 C UPAB: 19930902 The phase locked loop derives sample pulses from the edge changes in the...
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such...
According to an example embodiment, there is a testing device for testing a phase locked loop having...
Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in ac...
Abstract of US2006164137 A phase locked loop comprising a phase detector ( 100 ) for determining a p...
Techniques for a simple automated test approach for high performance fully embedded charge-pump phas...
Due to rapid advances in the speed and complexity of VLSI circuits, analog and mixed-signal circuit...
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an o...
This paper presents a voltage quality detection method based on a phase-locked loop (PLL) technique....
A phase locked loop wherein the voltage controlled oscillator is controlled by the output of a phase...
Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on...
An innovative approach for testing PLLs in open loop-mode is presented. Tbe operational method consi...
An innovative approach for testing PLLs in open loop-mode is presented. The operational method consi...
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such...
A method and apparatus for testing analogue or RF circuitry, wherein the power supply VDD is ramped ...
DE 2854039 C UPAB: 19930902 The phase locked loop derives sample pulses from the edge changes in the...
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such...
According to an example embodiment, there is a testing device for testing a phase locked loop having...
Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in ac...
Abstract of US2006164137 A phase locked loop comprising a phase detector ( 100 ) for determining a p...
Techniques for a simple automated test approach for high performance fully embedded charge-pump phas...
Due to rapid advances in the speed and complexity of VLSI circuits, analog and mixed-signal circuit...
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an o...
This paper presents a voltage quality detection method based on a phase-locked loop (PLL) technique....
A phase locked loop wherein the voltage controlled oscillator is controlled by the output of a phase...
Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on...
An innovative approach for testing PLLs in open loop-mode is presented. Tbe operational method consi...
An innovative approach for testing PLLs in open loop-mode is presented. The operational method consi...
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such...
A method and apparatus for testing analogue or RF circuitry, wherein the power supply VDD is ramped ...
DE 2854039 C UPAB: 19930902 The phase locked loop derives sample pulses from the edge changes in the...
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such...