Error Modeling for DAC Correction, a Broad View

This chapter reviews some of the DAC error mechanisms that can be counteracted by correction methods. The mismatch related amplitude and sampling errors of the DAC current cells are discussed. A model is proposed that explains the performance deterioration due to the amplitude and timing errors of the current cells. The timing errors are modeled as a composition of sampling and amplitude errors. This model helps explaining how the amplitude errors contribute to the timing errors and hence influence the DAC dynamic performance. Beyond this, other data-dependent error mechanisms are considered: the disturbance at the common source node of the current switches, charge feed-through, and disturbances on the power supply and bias wires. These secondary errors interact with the amplitude and sampling errors and form error mechanisms that cause DAC non-linearity. Since these errors depend on the transistor mismatch, the performance of the overall DAC design is bound to the specified spreads and tolerances of the used IC technology. The chapter defines the Error Transfer Function and its frequency dependence, which is further used for the proposed classification in Chap. 7.