ΣΔ Modulator Robustness

In the analysis of the ΣΔ modulator’s SQNR in Chap. 5, the circuits are assumed to have no imperfections. In reality, the performance of the circuits will come at the cost of resources (area and power). Trade-offs have to be made to come to a good performance-to-resource ratio which can be verified in a benchmark with other ΣΔ modulators. The benchmarking of modulators will be done in Chap. 8. In this chapter, the relation between architecture choices and circuit imperfections and their impact on the ΣΔ modulator performance and cost will be discussed. The subjects of discussion are technology, continuous-time vs. discrete time loop filter, feed-forward vs. feedback loop filter, gain accuracy, circuit noise, linearity, aliasing, excess loop delay. Furthermore, a significant part of this chapter is spent on clock jitter. The models in which a ps, rms time error is translated in an amplitude error are replaced by much more accurate phase noise based models. New equations that relate jitter on the clock to the modulator SNR are calculated for modulators with a 1-bit or multi-bit, switched current or switched capacitor DAC. It is shown that the new models very well match with measurements.