Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis

Cell-aware test (CAT) offers a high-quality test that explicitly targets potential cell-internal open and short defects. CAT requires to characterize library cells to determine which cell patterns can detect which cell-internal defects. Characterization is performed only once per library, but in today's implementations [1], [2] it is nevertheless a very time-consuming task, since it performs analog simulation on every library cell c, for every potential defect d, and with every cell pattern p. However, after the lengthy simulation, invariably a majority of the defect/pattern tuples (d, p) turns out to be undetectable. Often, an undetectable tuple (d, p) can be identified only on the basis of the topology of the cell's transistors netlist. We refer to this as logical undetectability. This paper presents an efficient algorithm that performs a structural analysis of library cells to identify all logically undetectable tuples (d, p), which then can be excluded from the time-consuming analog simulation. As our structural analysis is a lot faster than the analog simulation, their combination delivers significant speed-ups; for 476 standard cells from Cadence's GPDK045 library [3], the algorithm identified 47% of logically undetectable tuples.