A high-speed broadband programmable frequency divider chip is designed and implemented in 0.18μm SiGe BiCMOS process. The chip is based on the 2/3 dual-mode frequency divider, and integrates high-speed logic operation and reset control in the flip-flop to achieve continuous integer frequency division from 1 to 511. Taking SCFL DFF as basic units, it realizes wide-band operation and obtains a good input sensitivity range. The simulation results demonstrate that the operating frequency can cover 0.1GHz~22GHz, and the input sensitivity in the whole frequency band is lower than -20dBm
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
In this paper design and simulation of a 10 GHz, divide by 16…511 programmable frequency divider bas...
Abstract—Static frequency dividers are widely used technology performance benchmark circuits. Using ...
A high-speed broadband programmable frequency divider chip is designed and implemented in 0.18μm SiG...
The design of a high-speed wide-band high resolution programmable frequency divider is investigated....
Design of a digital dynamic divider in SiGe bipolar technology is presented in this paper. The propo...
Abstract—Frequency dividers play an important role in highspeed communications systems. In particula...
Abstruct- The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider...
The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presen...
A low-voltage programmable frequency divider with wide input frequency range is fabricated in standa...
A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. T...
A programmable frequency divider operating at input frequencies from DC to 80 GHz for the use in fra...
A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency syn...
High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. Thes...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
In this paper design and simulation of a 10 GHz, divide by 16…511 programmable frequency divider bas...
Abstract—Static frequency dividers are widely used technology performance benchmark circuits. Using ...
A high-speed broadband programmable frequency divider chip is designed and implemented in 0.18μm SiG...
The design of a high-speed wide-band high resolution programmable frequency divider is investigated....
Design of a digital dynamic divider in SiGe bipolar technology is presented in this paper. The propo...
Abstract—Frequency dividers play an important role in highspeed communications systems. In particula...
Abstruct- The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider...
The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presen...
A low-voltage programmable frequency divider with wide input frequency range is fabricated in standa...
A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. T...
A programmable frequency divider operating at input frequencies from DC to 80 GHz for the use in fra...
A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency syn...
High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. Thes...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
In this paper design and simulation of a 10 GHz, divide by 16…511 programmable frequency divider bas...
Abstract—Static frequency dividers are widely used technology performance benchmark circuits. Using ...