Low power Karnaugh map approximate adder for error compensation in loop accumulations

Approximate computing has recently emerged as a promising paradigm to achieve considerable energy savings at the expense of degraded computing accuracy. In this paper, an approximate adder is proposed to reduce the power consumption while providing minimal computation errors for loop accumulation, which is a crucial operation in various signal processing algorithms. The proposed adder is based on smart modification of Karnaugh map to generate compensation effect with loop accumulation. With the proposed approximate adder, the power consumption is reduced by up to 42.8% and 24.9% compared to fully-accurate adder and the previously published approximate adders, respectively, in an industrial 65-nm CMOS technology. Furthermore, the computation accuracy is enhanced by up to 31x with the proposed approximate adder compared with the previously published approximate adders. Using the product of normalized mean error distance (NMED) and power consumption as the Figure-of-Merit (FoM), the proposed approximate adder improves the FoM by up to 37.7x compared to the previously published approximate adders.