Fast-shared current transient response in high-precision interleaved inverters

A robust self-interleaving mechanism for paralleled hysteresis-current-controlled inverters is proposed, featuring sustained switching under all load conditions. A fast interleaving technique that can be applied when no clamping of the output voltage occurs is combined with a self-interleaving mechanism that ensures correct switching during output-voltage-clamping conditions. The self-interleaving mechanism was analyzed using the state-plane method, extended to multiple modules in parallel. A minimum switching frequency and maximum duty cycle are guaranteed under all load conditions, enabling the use of low-cost bootstrap circuits to drive the high-side switches. The interleaving approach results in reduced volume of the passive components and improved dynamic response. Simulations were conducted to verify the combined operation of both methods, and measurements were performed on a 2.8-kW prototype zero-voltage-switching inverter with a discrete hysteresis current controller