Predictive timing error calibration technique for RF current-streering DACs

Timing errors become more dominant in dynamic performance in high-resolution Radio Frequency DACs. It consumes a lot of power and area to reduce timing errors below picoseconds. To relax the requirements on circuit design and layout complexity, a predictive timing error calibration technique based on on-chip timing error measurement is demonstrated in this work. Matlab behavior level simulation shows that this on-chip calibration technique can improve the SFDR significantly in a 2GS/s DAC. Simulation results of a phase detector, the key circuit in this calibration technique, are given. The circuit is designed in a CMOS 90nm process