Design of hardware accelerators for demanding applications.

This paper focuses on mastering the architecture development of hardware accelerators. It presents the results of our analysis of the main issues that have to be addressed when designing accelerators for modern demanding applications, when using as an example the accelerator design for LDPC decoding for the newest demanding communication system standards. Based on the results of our analysis, we formulate the main requirements that have to be satisfied by an adequate accelerator design methodology, and propose a design approach which satisfies these requirements