A novel digital technique for efficient calibration of static errors in high-speed, high-resolution, multi-step ADCs is proposed. The parameter update within the calibration method is extended to include and correct effects of temperature and process variations. Additionally, to guide the verification process with the information obtained through monitoring process variations, expectation-maximization method is employed. The algorithm is evaluated on a prototype multi-step ADC converter with embedded dedicated sensors fabricated in standard single poly, six metal 0.09-樨 CMOS
Abstract—This paper describes a digital-domain self-calibration technique for multistage pipelined a...
This dissertation presents the design of three high-performance successive-approximation-register (S...
This thesis presents all-digital calibration algorithms for correcting static non-linearities in an ...
A novel digital technique for efficient calibration of static errors in high-speed, high-resolution,...
A novel digital technique for efficient calibration of static errors in high-speed, high-resolution,...
A novel digital technique for efficient calibration of static errors in high-speed, high-resolution,...
A novel digital technique for efficient calibration of static errors in high-speed, high-resolution,...
Abstract — A novel digital technique for efficient calibration of static errors in high-speed, high-...
This paper reports a new approach for debugging of the analog to digital converters based on process...
This paper reports a new approach for debugging of the analog to digital converters based on process...
This paper reports a new approach for debugging of the analog to digital converters based on process...
This paper reports a new approach for debugging of the analog to digital converters based on process...
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions ...
A high-speed, high-resolution analog-to-digital converter (ADC) is a key component in broadband comm...
A high-speed, high-resolution analog-to-digital converter (ADC) is a key component in broadband comm...
Abstract—This paper describes a digital-domain self-calibration technique for multistage pipelined a...
This dissertation presents the design of three high-performance successive-approximation-register (S...
This thesis presents all-digital calibration algorithms for correcting static non-linearities in an ...
A novel digital technique for efficient calibration of static errors in high-speed, high-resolution,...
A novel digital technique for efficient calibration of static errors in high-speed, high-resolution,...
A novel digital technique for efficient calibration of static errors in high-speed, high-resolution,...
A novel digital technique for efficient calibration of static errors in high-speed, high-resolution,...
Abstract — A novel digital technique for efficient calibration of static errors in high-speed, high-...
This paper reports a new approach for debugging of the analog to digital converters based on process...
This paper reports a new approach for debugging of the analog to digital converters based on process...
This paper reports a new approach for debugging of the analog to digital converters based on process...
This paper reports a new approach for debugging of the analog to digital converters based on process...
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions ...
A high-speed, high-resolution analog-to-digital converter (ADC) is a key component in broadband comm...
A high-speed, high-resolution analog-to-digital converter (ADC) is a key component in broadband comm...
Abstract—This paper describes a digital-domain self-calibration technique for multistage pipelined a...
This dissertation presents the design of three high-performance successive-approximation-register (S...
This thesis presents all-digital calibration algorithms for correcting static non-linearities in an ...