Mapping a VLIW x SIMD processor on an FGA : scalability and performance

This paper describes VPF, a VLIW SIMD processor architecture developed to demonstrate the possibilities and limitations of the modern FPGA devices with respect to vector processing. VPF is developed in a bottom-up manner, using some specific Xilinx Virtex-4 device features to achieve 200 MHz performance for vector widths up to 16 issuing one VLIW instruction per clock cycle. The theoretical peak performance of VPF is 1.2·10^9 vector operations per second. For classical real-world DSP benchmarks around 1...3·10^8 vector operations per second can be achieved