Digital Post-Correction of Open-Loop Track-and-Hold Circuits

The front-end track-and-hold (T&H) circuit is one of the most critical components of an analog-to-digital converter (ADC). Considering a pipelined ADC, it is known that the errors of each stage of the pipeline will be attenuated by the interstage amplifiers, however, the errors of the front-end T&H will be directly present in the output codes produced by the ADC. Because of this, the accuracy requirements for the front-end T&H are the most stringent of all sample-and-hold stages in the ADC. Recently, the design of open-loop T&H circuits is getting more and more attention. Advantages of open-loop circuits include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. However, a major disadvantage of open-loop circuits is their relatively poor linearity. Therefore, unless some correction technique is applied, the use of open-loop architectures is limited to converters with a low accuracy (up to 8-bit). Though some digital correction techniques for the improvement of the linearity of open-loop structures have been presented previously [1], [2], they are limited to specific implementations or spe- ci¯c types of non-linearity (e.g. third order distortion). In this paper, a general digital post-correction method is presented. This method improves the linearity of the front-end T&H circuit in the digital domain independent on the actual T&H design or the shape of the non-linearity. The method includes both a measurement procedure to determine the actual non-linearity and a correction algorithm. As it is not relying on accurate reference components, it can be integrated easily on-chip. The method was verified by simulations on a T&H circuit designed on transistor-level in a 0:18¹m technology, and shows that its linearity can be improved from 9.5-bit up to 13.5-bit, while operating at a sample frequency of 500MHz