We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays incurred by the interface. XDI specifications capture restrictions on the communication between circuit and environment, treating both parties equally. They can be visualized as state graphs where each arrow is labeled by a communication terminal and each state by a safety/progress label. We investigate various properties that can be extracted from XDI specifications: automorphisms, environment partitions, autocomparison matrix, and classifications of choice, order dependence, and nondeterminism. We introduce a distinction between static and dynamic output nondetermin...
International audienceGiven a discrete-state continuous-time reactive system, like a digital circuit...
The thesis elaborates a so-called queued testing framework for input/output transition systems (IOTS...
A case study in delay-insensitive circuit design is presented. A one bit wide stack is decomposed in...
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that c...
It is not always straightforward to implement a network that is robust enough to be functionally ind...
It is,not always straight forward to implement a network that is robust enough to be functionally in...
Deep submicron technology calls for new design techniques, in which wire and gate delays are account...
The correct functionality of quasi-delay-insensitive asynchronous circuits can be jeopardized by the...
ISBN 978-1-4244-9138-4International audienceThis paper presents a method to synthesize hardware func...
A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investi...
ISBN :978-0-387-73660-0Quasi delay insensitive circuits are functionally independent of delays in ga...
A novel process algebra is presented; algebraic expressions specify delay-insensitive circuits in te...
International audienceBy design, quasi delay-insensitive (QDI) circuits exhibit higher resilience ag...
Concurrent and distributed behaviour encompasses a wide range of ever evolving phenomena and feature...
ISBN: 07298-0610-3Quasi delay insensitive circuits are functionally independent of delays in gates a...
International audienceGiven a discrete-state continuous-time reactive system, like a digital circuit...
The thesis elaborates a so-called queued testing framework for input/output transition systems (IOTS...
A case study in delay-insensitive circuit design is presented. A one bit wide stack is decomposed in...
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that c...
It is not always straightforward to implement a network that is robust enough to be functionally ind...
It is,not always straight forward to implement a network that is robust enough to be functionally in...
Deep submicron technology calls for new design techniques, in which wire and gate delays are account...
The correct functionality of quasi-delay-insensitive asynchronous circuits can be jeopardized by the...
ISBN 978-1-4244-9138-4International audienceThis paper presents a method to synthesize hardware func...
A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investi...
ISBN :978-0-387-73660-0Quasi delay insensitive circuits are functionally independent of delays in ga...
A novel process algebra is presented; algebraic expressions specify delay-insensitive circuits in te...
International audienceBy design, quasi delay-insensitive (QDI) circuits exhibit higher resilience ag...
Concurrent and distributed behaviour encompasses a wide range of ever evolving phenomena and feature...
ISBN: 07298-0610-3Quasi delay insensitive circuits are functionally independent of delays in gates a...
International audienceGiven a discrete-state continuous-time reactive system, like a digital circuit...
The thesis elaborates a so-called queued testing framework for input/output transition systems (IOTS...
A case study in delay-insensitive circuit design is presented. A one bit wide stack is decomposed in...