ASCOM: Affordable Sequence-aware COntention Modeling in crossbar-based MPSoCs

Multicore interference that arises when several accesses contend for the same shared hardware resources poses a challenge to the already demanding consolidated verification and validation practice. The Sequence-Aware Pairing (SeAP) model approach exploits the parallelism granted by crossbars to derive tighter contention bounds. We show that SeAP suffers from scalability issues that hinders its applicability to more complex contention scenarios. We address SeAP limitations in terms of scalability by identifying two complementary techniques to reduce SeAP execution time requirements. We assess the proposed approaches to show how they effectively enable the application of SeAP to large sequences of accesses to the crossbar with limited impact on tightness, and scaling gracefully with the number of co-running cores.The research leading to these results has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No. 772773). This work has also been partially supported by Grant PID2019-107255GB-C21 funded by MCIN/AEI/ 10.13039/501100011033.Peer ReviewedPostprint (author's final draft