Compact transformer based power combination techniques for millimeter-wave CMOS power amplifiers

The strong demand on miniaturization of wireless communication systems has propelled the development of radio-frequency (RF) component integration in semiconductors. In the realm of millimeter-wave (mm-wave), the V-band centred at 60 GHz has been demonstrated to be the most promising frequency range for short range communication applications such as high data rate transfer systems. In fact, silicon-based 60 GHz chipsets with integrated power-amplifiers (PA) have become an economical choice for high density integration. As an indispensable building block in RF-front-end, compact PAs are highly sought after especially for low cost and high volume production. This dissertation presents novel designs of compact PAs using series, hybrid and parallel power-combining transformer techniques based on 65 nm low-power CMOS technology for V-band applications. In the first design, a special shielding technique is incorporated into a series combining transformer for diminishing phase and amplitude discrepancies of the combined waves in differential drive PA. A new layout configuration of high quality factor (Q) inductor integrated with CMOS transistor source is demonstrated. To characterize this circuit topology, admittance matrix condensation algorithm is proposed, validated and then used for seeking the optimum inductance range. Following that, the nonlinearity of CMOS transistor with inductive source degeneration (ISD) is studied using Volterra kernels in mm-wave frequency range. Based on these techniques, the fabricated PA has a compact size of 693×652 µm2. Comparing to the state-of-the-art, the measured gain is above 10 dB at a wide bandwidth of 41-61 GHz. It is also capable of delivering high saturated power of 15.2 dBm at V-band. The second differential PA utilizes an innovative concentric winding technique to realize differential 2-way parallel splitting and 4-way hybrid combining transformers with compact size. The implementation strategies of the hybrid combining transformer are acquired by investigating its coupling effect. When the combiner is connected with active devices, its nonlinear behaviors are studied. Using this winding technique, the area consumption of passive matching networks is largely saved and hence the chip area can be more efficiently used in a multi-stage PA architecture. During design phase of cascading stages, the active device is analyzed with transformer matching topology for wideband stability and gain flatness. With a compact size of 0.32 µm2, the implemented PA in measurement achieves a high gain of 26.6 dB and delivers a high output power of 19.7 dBm at 60 GHz. The according 3-dB bandwidth covers a wide range of 51 GHz to 67 GHz. This PA also demonstrates the best performance in terms of gain-bandwidth product and figure of merit among the most advanced V-band CMOS PAs. Finally, a balun for power-combining is devised on the proposed principle of concentric winding for realizing high power density in a single-ended PA. This configuration concurrently accomplishes balanced-unbalanced conversion and parallel power splitting/combining. To calculate its power combination efficiency under the circumstance of input/output wave components with various phases and amplitudes, a computation method has been developed accordingly. Using the proposed power combining balun, the designed PA occupying only 0.10 µm2 chip core area achieves the highest power density of 269.15 mW/mm2 among the state-of-the-art 60 GHz CMOS PAs.DOCTOR OF PHILOSOPHY (EEE