UVM-based PCIe interrupt model for verification of networking platform IP

Nowadays, callback are widely applied in interrupt function for verification of a Network System IP. Engineers manually trigger the interrupt by call that function, which is not reusable and application scenario is specific. This means there is currently no appropriate interrupt model for verification of Network system IP at both the IP and SoC levels. This dissertation intends to establish an interrupt model that cannot only solve the existing problems, the proposed model also can be more generic and applied to other verification situation, like chip top validation. This intended interrupt model will be constructed and developed on the basis of the universal verification methodology (UVM), which provides the primary object and components hierarchy to the testbench. Besides, System Verilog is the applied hardware verification description language whose objected-oriented characteristic complies with UVM. The two operate hand-in-hand to assure reusability and standardisation. To ensure that the intended interrupt model works well, two other models, one for imitating design under test (DUT) and another for mimicking the behaviour of memory, are created. With simulation, it shows that the interrupt model can trigger the interrupts successfully with various delay requirements and the design model can process the related registers and memories, i.e., read, write, etc. in the correct time sequence. All simulations are supported by Synopsis VCS and waveform analysis is evaluated by VerdMaster of Science (Integrated Circuit Design