Design of time-predictable architecture and DDR memory bank allocation for COTS multi-cores

An increasing trend in the chip manufacturing industry is the adoption of multi-core processors. This overwhelming trend of using Commercial Off-The-Shelf (COTS) multi-core processors has benefited most of the industries that require high computing performance at low power and greater efficiency. However, real-time systems are those systems where not only the correctness of execution is critical but also the time at which this execution occurs is equally critical. The multi-core processors offer a very high computing performance owing to the increased number of processing cores, but do not guarantee a predictable Worst-Case Execution Time (WCET), which is defined as the maximum time an application can take to execute on a given hardware. This uncertainty in the estimation of the WCET arises from a multitude of challenges which are inherently present in the multi-core architecture. As a first step, these challenges are identified and then further focused on exploring a representative multi-core processor. The primary challenges identified in this thesis are related to the sharing of hardware components in the multi-core architecture which includes the Double Data Rate (DDR) memory and its controller, caches and system bus. A detailed architecture analyses of a COTS multi-core is performed along with a series of experiments which help to understand and quantify the unpredictability arising due to the sharing of hardware resources. This study not only helps to understand the challenges but also the severity of each challenge. As a next step, to mitigate this primary challenge of shared memory subsystem in the multi-cores, a novel hybrid System On Chip (SoC) architecture is proposed which couples COTS multi-core with a Field Programmable Gate Array (FPGA). The proposed architecture is designed on the Xilinx Zynq 706 platform. The key feature of this proposed architecture is that the shared hardware components which causes the unpredictability inside the multi-core are disabled and are designed separately on the FPGA to aid predictable execution of applications. The thesis specifically focuses on one of the components in the shared memory subsystem, which is the DDR memory and its controller. A predictable memory controller is designed for this architecture to show that the ARM A9 multi-core can be coupled with the custom designed memory controller on the FPGA. The thesis also shows that the latency on the FPGA can be bounded theoretically and hence this architecture aids in predictable execution of applications. As a final step, the thesis focuses on the DDR memory and its controller and address one of the key challenges which is DDR memory bank allocation to the cores. Although the execution time of an application can be bounded in a predictable memory controller, it is important to allocate only the required number of banks to the cores such that the worst-case execution time requirement of the application is satisfied. This allocation determines the utilization of the DDR memory. Hence, it is important that the number of banks should not be overloaded for any application. The thesis specifically focus on two scenarios. One, where the banks of the DDR are shared by the cores and the other where the banks are private to the cores. In each of the scenario, an optimal bank allocation policy is presented. The key significance of this contribution is the fact that the algorithms presented are optimal and always return the best allocation whenever feasible. Thus, in this dissertation an outline to use the multi-cores in a predictable manner for real-time systems has been provided.Doctor of Philosoph