Efficient architectures for computation of binary logarithm

Logarithmic Number System (LNS) is often used in digital signal processing to simplify complex arithmetic operations. LNS requires data to be converted into the logarithmic domain, i.e., logarithmic conversion. The thesis studies the VLSI architectures for logarithmic conversion. The existing Mitchell-based logarithmic conversion methods are first investigated, specifically the parameters that impact the accuracy and hardware merits are analyzed and an architectural model is established. Subsequently, a novel method, named the Unified Mitchell-based Approximation method (UMA), is proposed to obtain, for any given accuracy requirement up to 14 bits, a logarithmic converter optimized in area-delay product (ADP). The experimental results show that the designs obtained have better ADPs than those by the existing Mitchell-based methods, with eight of the thirteen designs achieving better ADP by more than 50%. The designs with conversion accuracy of 12, 13 and 14 bits, which are not currently available, are also obtained. Approaching the Mitchell-based methods from a fresh angle, a novel method named the Range Mapping (RM) is proposed to map and compress the entire range of approximation, [1,2), of the logarithm function into only about one third of the original range. As a result, it enhances the effectiveness of the piecewise linear approximation for improving the accuracy. When a newly proposed 4-region piecewise linear approximation is developed for the compressed range, the maximum absolute error and maximum absolute error percentage are reduced by 15.0% and 25.0% respectively when compared to the best existing results. Furthermore, applying the UMA on the compressed range, optimized converters can be obtained for accuracy up to 18 bits. For accuracy requirement higher than 18 bits, a new method known as the integrated Add-Table Lookup-Add (iATA) is proposed to reduce table (memory) size by abandoning the central difference formulation (used in the existing ATA method) for approximating the first derivatives in the Taylor series of the function. Three additional techniques, namely the carry select technique, the symmetry property exploitation and the unequal partitioning of input with the aid of error analysis, are integrated for further memory optimization. The experimental results show that iATA achieves a memory saving of 87.22% when compared to the best existing result. The thesis details the development of the three methods, their mathematical formulations, the hardware architectures obtained, the performance evaluations of the architectures and their comparisons with the state-of-the-art designs.DOCTOR OF PHILOSOPHY (EEE