Dual-rail CMOS logic, also called as differential CMOS logic handles both true and complementary signals at any time. Various dual-rail CMOS logic styles have been designed and explored, including differential cascade voltage switch logic (DCVSL), complementary pass-transistor logic (CPL), differential cascade voltage switch with pass-gate (DCVSPG) logic, and double pass-transistor logic (DPL). These kinds of dual-rail CMOS logic will be simulated by Cadence. The simulation results and application of the dual-rail CMOS circuits in full adder are also presented in this dissertation, which will be tested by simulating circuits with Cadence.Master of Science (Electronics
A new multiple-valued circuit based on dual-rail differential logic is proposed for crosstalk noise ...
A new CSDL circuit is proposed which reduces the number of transistors and input signals required co...
This report provides a quick reference of ac-coupling techniques for interfacing between different l...
For a few decades, CMOS has been well known for a quite efficient design methodology. With its uniqu...
Designing high-speed low-power circuits with CMOS technology has been a major research problem for m...
We present a new logic family, Differential Current Switch Logic (DCSL) for implementing clocked CMO...
[[abstract]]A CMOS differential logic, called the latched CMOS differential logic (LCDL), is propose...
Power consumption is always the key problem for the digital circuit design. Also, information leaked...
The Differential Cascode Voltage Switch Logic (DCVSL) is a CMOS circuit technique which has potentia...
Dual mode logic (DML) with both static and dynamic modes is able to solve severe delay of CMOS in lo...
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
Cascode voltage switch (CVS) logic is a CMOS circuit technique which has potential advantages over c...
A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, maki...
In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) ...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
A new multiple-valued circuit based on dual-rail differential logic is proposed for crosstalk noise ...
A new CSDL circuit is proposed which reduces the number of transistors and input signals required co...
This report provides a quick reference of ac-coupling techniques for interfacing between different l...
For a few decades, CMOS has been well known for a quite efficient design methodology. With its uniqu...
Designing high-speed low-power circuits with CMOS technology has been a major research problem for m...
We present a new logic family, Differential Current Switch Logic (DCSL) for implementing clocked CMO...
[[abstract]]A CMOS differential logic, called the latched CMOS differential logic (LCDL), is propose...
Power consumption is always the key problem for the digital circuit design. Also, information leaked...
The Differential Cascode Voltage Switch Logic (DCVSL) is a CMOS circuit technique which has potentia...
Dual mode logic (DML) with both static and dynamic modes is able to solve severe delay of CMOS in lo...
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
Cascode voltage switch (CVS) logic is a CMOS circuit technique which has potential advantages over c...
A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, maki...
In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) ...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
A new multiple-valued circuit based on dual-rail differential logic is proposed for crosstalk noise ...
A new CSDL circuit is proposed which reduces the number of transistors and input signals required co...
This report provides a quick reference of ac-coupling techniques for interfacing between different l...