Add to ORKGIn memory computing has become popular recently. It not only could accelerate the AI application on hardware, but also could solve the Neumann problem. In this field, digital SRAM design for machine learning has received a lot of attention due to its easy design and high accuracy characteristics. In this paper, a 4k weight-selective digital SRAM design is implemented with improvements on Bitcell and Adder Tree. It uses TG logic in the design to improve the speed and eliminate power consumption. The weight-Selective function is used to adapt to the different complexity of the calculation. The simulation is done by using the TSMC65LP process. The Bitcell Array is 64x64, GOPS is 409.6 and the frequency is 200MHz.Master of Science (Electronics
International audienceThis paper presents a new methodology for automating the Computational SRAM (C...
As the computational complexity of applications on the consumer market, such as high-definition vide...
This paper presents the design of the peripheral circuits required to implement a memory array using...
The well-known Moore's Law is about to end after CMOS devices using 7nm process technology are widel...
DoctorThis dissertation presents three case studies on the design of smart SRAM that is capable of ...
In order to cope with the storage wall of the von Neumann computing architecture, the computing in-m...
The Internet data has reached exa-scale (1018 bytes), which has introduced emerging need to re-exami...
With the increase in computational parallelism and low-power Integrated Circuits (ICs) design, neuro...
The objective of the research was to design and test an SRAM system which can meet the performance c...
Abstract:Optimization of SRAM (Static Random Access Memory) array design can be done at three domain...
This report presents state-of-the-art In-memory Computing (IMC) works using SRAM. A brief introducti...
The proliferation of embedded Neural Processing Units (NPUs) is enabling the adoption of Tiny Machin...
SRAM has become the most important memory structure in storage due to its small size and high speed....
Digital computation has penetrated diversity of applications such as audio visual communication, bio...
The aim of this project is to develop customizable hardware that can perform Machine Learning tasks....
International audienceThis paper presents a new methodology for automating the Computational SRAM (C...
As the computational complexity of applications on the consumer market, such as high-definition vide...
This paper presents the design of the peripheral circuits required to implement a memory array using...
The well-known Moore's Law is about to end after CMOS devices using 7nm process technology are widel...
DoctorThis dissertation presents three case studies on the design of smart SRAM that is capable of ...
In order to cope with the storage wall of the von Neumann computing architecture, the computing in-m...
The Internet data has reached exa-scale (1018 bytes), which has introduced emerging need to re-exami...
With the increase in computational parallelism and low-power Integrated Circuits (ICs) design, neuro...
The objective of the research was to design and test an SRAM system which can meet the performance c...
Abstract:Optimization of SRAM (Static Random Access Memory) array design can be done at three domain...
This report presents state-of-the-art In-memory Computing (IMC) works using SRAM. A brief introducti...
The proliferation of embedded Neural Processing Units (NPUs) is enabling the adoption of Tiny Machin...
SRAM has become the most important memory structure in storage due to its small size and high speed....
Digital computation has penetrated diversity of applications such as audio visual communication, bio...
The aim of this project is to develop customizable hardware that can perform Machine Learning tasks....
International audienceThis paper presents a new methodology for automating the Computational SRAM (C...
As the computational complexity of applications on the consumer market, such as high-definition vide...
This paper presents the design of the peripheral circuits required to implement a memory array using...